Hierarchical code[1]
Description
Member of a family of \([[n,k,d]]\) qubit stabilizer codes resulting from a concatenation of a constant-rate QLDPC code with a rotated surface code. Concatenation allows for syndrome extraction to be performed on a 2D geometry while maintining a threshold at the expense of a logarithmically vanishing rate. The growing syndrome extraction circuit depth allows known bounds in the literature to be weakened [2,3].
Rate
Rate vanishes as \(\Omega(1/\log(n)^2)\).
Decoding
Decoding is performed as in a standard concatenated code using a decoder for the inner code and outer code. The syndrome extraction circuit depth for the outer code is optimized using a permutation routing algorithm [4]. The bilayer architecture allows for logical entangling gates between logical surface-code patches.Soft output decoding [5].
Fault Tolerance
2D geometrically local syndrome extraction circuits of depth \(O(\sqrt{n}/R)\) that utilize Clifford and SWAP gates of range \(R\) and that require order \(O(n)\) data and ancilla qubits. Such parameters (including a range of one) are possible while maintaining a threshold because of the concatenation step. This reduces the noise that would otherwise accumulate within a growing-depth syndrome extraction circuit. A key idea is that constant-depth syndrome extraction is not a necessary condition for fault-tolerance.
Threshold
Threshold exists for the locally decaying error model; see [1; Thm. 1.3]. However, the logical error rate below threshold falls super-polynomially (as opposed to exponentially) with the code distance. The code family possesses a threshold equal to that of surface codes given by tuning the inner code size for any fixed physical error rate.
Parents
- Qubit stabilizer code
- Quantum low-density parity-check (QLDPC) code
- Concatenated qubit code — Hierarchical codes are concatenations of constant-rate QLDPC (outer) codes with (inner) rotated surface codes. The block length of the inner code is picked to grow logarithmically with the block length of the outer code.
Child
- Rotated surface code — Hierarchical codes are concatenations of constant-rate QLDPC codes with rotated surface codes.
References
- [1]
- C. A. Pattison, A. Krishna, and J. Preskill, “Hierarchical memories: Simulating quantum LDPC codes with local gates”, (2023) arXiv:2303.04798
- [2]
- N. Delfosse, M. E. Beverland, and M. A. Tremblay, “Bounds on stabilizer measurement circuits and obstructions to local implementations of quantum LDPC codes”, (2021) arXiv:2109.14599
- [3]
- N. Baspin, O. Fawzi, and A. Shayeghi, “A lower bound on the overhead of quantum error correction in low dimensions”, (2023) arXiv:2302.04317
- [4]
- F. Annexstein and M. Baumslag, “A unified approach to off-line permutation routing on parallel networks”, Proceedings of the second annual ACM symposium on Parallel algorithms and architectures - SPAA ’90 (1990) DOI
- [5]
- N. Meister, C. A. Pattison, and J. Preskill, “Efficient soft-output decoders for the surface code”, (2024) arXiv:2405.07433
Page edit log
- Christopher A. Pattison (2023-06-02) — most recent
- Victor V. Albert (2023-03-12)
Cite as:
“Hierarchical code”, The Error Correction Zoo (V. V. Albert & P. Faist, eds.), 2023. https://errorcorrectionzoo.org/c/hierarchical