Directional tile code[1]
Description
Member of a family of tile codes on a planar square grid whose \(X\)- and \(Z\)-type stabilizer generators are supported on one connected string traced by a directional word \(\mathfrak{D}=\vec{d}_1\vec{d}_2\cdots\vec{d}_w\) of steps in the four lattice directions. The same word is the schedule of a nearest-neighbor circuit that measures the generators. Each step of the word applies one layer of CXSWAP gates, and each gate both adds a data qubit’s parity to a check qubit and moves that check qubit one site along the walk [1].
A weight-\(w\) generator is thus measured in depth \(w\), with the check-data connectivity generated by moving the check qubits rather than built into the device. The CXSWAP gate is the iSWAP gate up to single-qubit Clifford gates, and iSWAP is native to superconducting devices, the platform the family is designed for. Data qubits sit on lattice edges, \(X\)-type check qubits on vertices, and \(Z\)-type check qubits on plaquettes. At step \(i\), every check qubit interacts with its neighbor in direction \(\vec{d}_i\), acting as the control of the CX for \(X\)-type checks and as the target for \(Z\)-type checks. After \(w\) steps each check qubit has visited every data qubit of its tile and is measured. Consecutive rounds alternate the word and its inverse, which returns every qubit to its starting position. Where the planar embedding leaves a gap between a check qubit and the next data qubit of its walk, a routing qubit prepared in \(|0\rangle\) fills it. On a routing qubit the CXSWAP gate acts as a plain SWAP. Routing qubits are needed only near the boundary, so their number is of order \(O(\sqrt{n})\) [1].
A code is built by placing the \(X\)- and \(Z\)-tile pair at every vertex of an \(M\times N\) grid of anchors and placing boundary tiles of each type separately. Edges covered by tiles of only one type are then pruned, together with any tile emptied by the pruning. The remaining edges are the data qubits and the remaining anchors are the check qubits. Commutation of the two tiles follows from the tile-code mutual condition. Determinism of the measurement circuit requires one more condition on the word: every displacement vector between two edges of the string with odd vertical displacement must occur an even number of times [1]. Directional tile codes are the open-boundary counterparts of directional codes, which apply the same word on a torus.
The weight-\(11\) word \(N^2E^2SESE^2N^2\) yields a \([[323,14,15]]\) code with \(kd^2/n=9.75\), nearly an order of magnitude above that of the rotated surface code [1]. See Ref. [1; Table II] for codes from words of weight \(7\) to \(13\).
Protection
Logical operators have a boundary-to-boundary structure like those of the surface code. The \(X\)- and \(Z\)-type distances are therefore controlled by the two bulk dimensions \(M\) and \(N\) of the anchor grid, respectively [1]. An unbalanced anchor grid yields unbalanced distances, such as a \([[611,20,d_X\leq 84,d_Z=7]]\) code [1].Rate
The code-parameter efficiency \(kd^2/n\) reaches 9.76 for the \([[248,20,11]]\) code [1]. Since the implementation needs routing qubits, performance is also measured by the circuit-efficiency ratio \(\eta_{\text{circ}}=k\,n_{\text{RSC}(d)}/n_{\text{circ}}\). This ratio compares the full layout against \(k\) rotated surface-code patches, using \(n_{\text{RSC}(d)}=2d^2-1\). All data, check, and routing qubits are counted in \(n_{\text{circ}}\). The ratio reaches 7.89 for the \([[323,14,15]]\) code [1].Transversal and Permutation-Based Gates
Logical Pauli operators are given by the canonical symplectic basis of tile codes, whose representatives are supported near the lattice boundaries and are generated by a finite cellular-automaton rule [1,2].Decoding
Routing qubits can be measured during the walk. Nontrivial outcomes flag faults along the routing path and are supplied to the decoder, which improves decoding at relatively high physical error rates [1].Fault Tolerance
Including check-qubit preparation and measurement, one syndrome-extraction round has depth \(w+2\), independent of the code size and optimal for stabilizer generators of weight \(w\) [1].Under uniform circuit-level depolarizing noise at physical error rate \(10^{-3}\), the best layouts reduce the per-logical per-round logical error rate by up to three orders of magnitude [1]. The comparison is against rotated surface codes encoding the same number of logical qubits, at a comparable footprint of about 30 circuit qubits per logical qubit [1].Faults on routing qubits propagate in a bounded way, since each data or check qubit participates in at most \(w\) two-qubit interactions per round [1].Cousins
- Directional code— Directional tile codes are the open-boundary (planar) analogues of directional codes, in the same way that tile codes are the open-boundary analogues of BB codes [1]. A directional tile code can equivalently be viewed as an open-boundary patch cut from a directional code, or as a planar tessellation by connected-string tiles [1]. Preserving the ordered walk on the open patch is what keeps every bulk and boundary stabilizer generator measurable by the same nearest-neighbor dynamics.
- 2D color code— The boundary-dominated routing overhead of directional tile codes is analogous to the routing overhead established for color-code circuits built from CXSWAP gates [3].
Primary Hierarchy
References
- [1]
- B. Gu, T. Noszko, V. Steffan, J. N. Eberhardt, J. Roffe, J. Eisert, and S. Koutsioumpas, “Nearest-neighbour gates are all you need: High-rate quantum low-density parity-check codes on a planar grid”, (2026) arXiv:2606.19482
- [2]
- N. P. Breuckmann, S. H. Choe, J. N. Eberhardt, F. R. F. Pereira, and V. Steffan, “Logical Operators and Derived Automorphisms of Tile Codes”, (2025) arXiv:2511.14589
- [3]
- S. Yoshida, C. Gidney, M. McEwen, and A. Zalcman, “Low Depth Color Code Circuits with CXSWAP gate”, (2025) arXiv:2510.00370
Page edit log
- Victor V. Albert (2026-09-26) — most recent
- Victor V. Albert (2026-08-26)
Cite as:
“Directional tile code”, The Error Correction Zoo (V. V. Albert & P. Faist, eds.), 2026. https://errorcorrectionzoo.org/c/directional_tile, arXiv:2606.11484