Description
A \([[k(k+1)/2,k]]\) QLDPC CSS code whose physical qubits store logical bits and their pairwise parities. It was originally designed to convert the long-range interactions of a quantum annealer into local constraints [1,2]. Diagonal logical gates become physical single-qubit \(Z\)-rotations at arbitrary angle [3].
Its stabilizer group is generated by \(Z\)-type parity constraints, and each logical \(X\) operator is supported on a logical line, the set of all physical qubits whose label contains a given logical index. The code becomes a universal quantum computing architecture once a row of data qubits, one per logical qubit, is added [3]. An extension maps more general models onto the same lattice [4].
For \(k\) logical qubits, the layout with data qubits consists of one data qubit per logical qubit and one parity qubit per pair of logical qubits [3,5]. The data qubit \((i)\) satisfies \(\overline{Z}_i = Z_i\), while the parity qubit \((ij)\) satisfies \(\overline{Z}_i\overline{Z}_j = Z_{ij}\). The stabilizer group is generated by the \(k(k-1)/2\) weight-three checks \(Z_i Z_j Z_{ij}\), one per pair of logical qubits. Physical qubits can be identified with the vertices and edges of the complete graph \(K_k\), with one check per edge [5]. The original formulation [1] contains only parity qubits, and is the same code with one fewer logical qubit. Fixing a reference logical index and identifying each parity qubit whose label contains that index with a data qubit maps the two formulations onto each other.
Protection
The \(X\)-distance is the number of physical qubits in the shortest logical line, which is \(k\) for the layout with data qubits [3]. Up to \(\lfloor (d_x-1)/2 \rfloor\) simultaneous bit-flip errors can be corrected [3]. Every logical \(Z\) operator has a weight-one representative on a data qubit, so phase errors are not protected.Encoding
Arbitrary quantum states [6].Parity qubits are added or removed one at a time by two CNOT gates from the qubits of the corresponding constraint [3]. This allows partial encoding and decoding during a computation, and switching between layouts with different numbers of parity qubits [3].Any \(k\)-qubit graph state can be prepared in the LHZ encoding in circuit depth at most \(k+3\) with \(2k(k-1)\) CNOT gates [7].Encoding circuit of depth \(k+1\), obtained by commuting and cancelling the CNOT gates of the iterative procedure [3]. The reversed sequence decodes.Transversal and Permutation-Based Gates
Logical operators are \(\overline{Z}_i = Z_i\) and \(\overline{X}_i = \prod_{A \ni i} X_A\), the product running over every physical qubit whose label contains \(i\).Diagonal logical gates are physical single-qubit \(Z\)-rotations at arbitrary angle [3]. A rotation on the parity qubit \((ij)\) is a logical two-qubit diagonal rotation on logical qubits \(i\) and \(j\). The logical controlled-phase gate is the depth-one product \(\overline{\mathrm{CP}}^{(i,j)}_{\phi}=R_z^{(i)}(\phi/2)R_z^{(ij)}(-\phi/2)R_z^{(j)}(\phi/2)\) [3].One layer of physical \(S\) gates and their powers realizes every addressable logical \(S\) and CZ gate, with \(\overline{S}_i=S_i\) and \(\overline{\mathrm{CZ}}_{ij}=S_i S_j S_{ij}^{\dagger}\) [5]. The code thus realizes the full group \(\mathcal{U}(2k,2)=\langle S_k,\mathrm{CZ}_k\rangle\) of addressable diagonal Clifford gates by transversal single-qubit Clifford gates, at the minimum possible block length \(n=k(k+1)/2\), of order \(\Theta(k^2)\) [5].Gates
Logical \(X\)-rotations use a chain of \(2(k-1)\) CNOT gates along a logical line together with one physical \(X\)-rotation [3,7]. The circuit depth is \(2\lceil k/2 \rceil+1\) for \(k>4\) [3]. Together with logical \(Z\)-rotations and controlled-phase gates, they form a universal gate set [3].Decoding
BP decoder [2].Cousin
- Concatenated cat code— LHZ parity-codes have been concatenated with cat codes [8].
Primary Hierarchy
References
- [1]
- W. Lechner, P. Hauke, and P. Zoller, “A quantum annealing architecture with all-to-all connectivity from local interactions”, Science Advances 1, (2015) DOI
- [2]
- F. Pastawski and J. Preskill, “Error correction for encoded quantum annealing”, Physical Review A 93, (2016) arXiv:1511.00004 DOI
- [3]
- M. Fellner, A. Messinger, K. Ender, and W. Lechner, “Universal Parity Quantum Computing”, Physical Review Letters 129, (2022) arXiv:2205.09505 DOI
- [4]
- K. Ender, R. ter Hoeven, B. E. Niehoff, M. Drieb-Schön, and W. Lechner, “Parity Quantum Optimization: Compiler”, Quantum 7, 950 (2023) arXiv:2105.06233 DOI
- [5]
- J. M. Koh, S. Majidy, A. Chakraborty, A. Gong, S. J. S. Tan, and N. Y. Yao, “Achieving the limits of automorphism gates”, (2026) arXiv:2609.19250
- [6]
- A. Messinger, M. Fellner, and W. Lechner, “Constant Depth Code Deformations in the Parity Architecture”, 2023 IEEE International Conference on Quantum Computing and Engineering (QCE) 120 (2023) arXiv:2303.08602 DOI
- [7]
- M. Fellner, A. Messinger, K. Ender, and W. Lechner, “Applications of universal parity quantum computation”, Physical Review A 106, (2022) arXiv:2205.09517 DOI
- [8]
- A. Messinger, V. Torggler, B. Klaver, M. Fellner, and W. Lechner, “Fault-tolerant quantum computing with the parity code and biased-noise qubits”, Physical Review Applied 23, (2025) arXiv:2404.11332 DOI
Page edit log
- Victor V. Albert (2026-09-19) — most recent
- Victor V. Albert (2026-06-08)
- Victor V. Albert (2024-04-21)
Cite as:
“Lechner-Hauke-Zoller (LHZ) code”, The Error Correction Zoo (V. V. Albert & P. Faist, eds.), 2026. https://errorcorrectionzoo.org/c/lhz, arXiv:2606.11484